The ’HC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR)
input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is
high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered.
If both clocks are connected together, the shift
register always is one clock pulse ahead of the
storage register.
https://www.sparkfun.com/datasheets/IC/SN74HC595.pdf
https://www.sparkfun.com/datasheets/IC/SN74HC595.pdf
